1. Field of the Invention
Embodiments of the present invention relate generally to video processing and more specifically to reusing memory addresses in a graphics system.
2. Description of the Related Art
Unless otherwise indicated herein, the approaches described in this section are not prior art to the claims in this application and are not admitted to be prior art by inclusion in this section.
For the ease of memory management and the sharing of limited physical memory resources, some graphics systems utilize a virtual addressing scheme for memory accesses. The virtual addressing scheme can be costly, because it necessarily involves the process of mapping a virtual memory address to a physical memory address, which is commonly referred to as “address translation.” One technique to reduce, but not to eliminate entirely, the address translation time is to cache certain virtual memory address and physical memory address information in a special buffer, the translation-lookaside buffer (“TLB”). Specifically, one type of TLB entry contains a virtual page number that has been recently accessed for translation as a tag and a physical page number as part of the payload data. As an illustration, FIG. 1 is a conceptual diagram of a TLB, such as TLB 100. TLB 100 has a number of entries, such as entry 102. Each entry includes multiple fields, two of which are the tag field and the physical page number field, as shown in FIG. 1. Thus, if virtual page number 106 of a requested virtual memory address, such as 104, matches one of the tags in TLB 100, such as 110, then physical page number 112 together with page offset 108 formulates physical memory address 114.
TLB 100 is an expensive hardware resource, requiring a random access memory (RAM), often of significant size, associative lookup logic for matching requests against cached RAM entries, and usually nontrivial logic for handling hits to pages that previously missed and are still being fetched. In a graphics system with many clients, multiple address translations may need to be performed simultaneously, potentially requiring multiple TLBs.
As the foregoing illustrates, what is needed in the art is a way to minimize the instances of a TLB in a graphics system to reduce hardware cost, while either maintaining or improving overall throughput.